1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a voltage generating circuit which compensates and outputs an output voltage in a case where operation requiring an output voltage of a predetermined level is continuously performed, and a semiconductor memory device having the same.
2. Description of the Related Art
In a typical semiconductor memory device, a memory cell array is comprised of a plurality of banks to make a data input/output (IO) process faster. The data IO process is performed through a process for activating or precharging a word line and a process for sensing and amplifying signals of bit line pair.
In the semiconductor memory device with such a multi-bank structure, in order to prevent a size of the semiconductor memory device from being too large as the number of banks is increased, a high voltage generating circuit for activating the word line, a precharge circuit for precharging the word line, and an internal voltage generating circuit for performing a bit line sensing operation are shared by a plurality of banks. However, the conventional semiconductor memory device has a problem that the high voltage generating circuit, the precharge circuit and the internal voltage generating circuit may not be supplied with sufficient voltage needed for their operation as the semiconductor memory device operates at high speed.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device with a multi-bank structure. The semiconductor memory device of FIG. 1 includes a memory cell array 10, a row decoder 20, a column decoder 30, and an internal voltage generating portion 40. The memory cell array 10 is comprised of a plurality of banks BANK0 to BANKn, and each bank includes a plurality of bit line sense amplifiers BLSA.
In FIG. 1, AIVC denotes an internal power voltage needed for sensing or amplifying data of a memory cell, PSE0 to PSEn denote bit line sense enable signals for operating the bit line sense amplifiers BLSA, RASB denotes a row activation command input from the external portion, and BA0 to BAm denote bank address signals input from the external portion.
Functions of the components FIG. 1 are described below.
The memory cell array 10 is comprised of a plurality of memory cells (not shown) and stores or outputs data in response to a command and an address signal which are input from the external portion. The bit line sense amplifiers BLSA in the memory cell array 10 senses or amplifies data transmitted to/from the memory cell (not shown) in response to the bit line sense enable signals PSE0 to PSEn. The row decoder 20 outputs the bit line sense enable signals. PSE0 to PSEn for operating the bit line sense amplifiers BLSA in response to the row activation command RASB and the bank address signals BA0 to BAm. The column decoder 30 activates a column selecting signal in response to a column address signal input from the external portion. The internal voltage generating portion 30 supplies a plurality of bit line sense amplifiers BLSA with the internal power voltage AIVC in response to the bit line sense enable signals PSE0 to PSEn.
FIG. 1 shows that the internal power voltage generating portion 40 is arranged in the column decoder 30, but the internal power voltage generating portion 40 may be arranged in a conjunction region where the row decoder 20 and the column decoder 30 meet.
Even though not shown in FIG. 1, a peripheral circuit region which includes the high voltage generating circuit for outputting a high voltage needed to activate the word line and the precharge voltage generating portion for outputting a precharge voltage needed to precharge the word line are arranged below the column decoder 30. As described above, the high voltage output from the high voltage generating circuit and the precharge voltage output from the precharge voltage generating circuit are commonly applied to a plurality of banks BANK0 to BANKn.
FIG. 2 is a block diagram illustrating part of the memory cell array of the semiconductor memory device of FIG. 1. In FIG. 2, BL and BLB denote a bit line pair, WL denotes a word line, MC denote a memory cell, BLSA denotes a bit line sense amplifier, WDR denotes a word line driver, PRECH denotes a precharge circuit, AIVC denotes an internal power voltage output from the internal power voltage generating portion 40, Vpp denotes a high voltage output from the high voltage generating portion, Vbb denotes a precharge voltage output from the precharge voltage generating circuit, PSE0 denotes a bit line sense enable signal, and PRC0 denotes a precharge signal.
Functions of the components of FIG. 2 and operation of the memory cell array are described below.
The word line driver WDR activates the word line WL to the high voltage Vpp in response to the bit line sense enable signal PSE0. The bit line sense amplifier BLSA senses and amplifies data of the bit line pair BL, BLB using the internal power voltage AIVC in response to the bit line sense enable signal PSE0. The precharge circuit PRECH precharges the word line WL to the precharge voltage Vbb in response to the precharge signal PRC0.
That is, when the bit line sense enable signal PSE0 is activated, the word line WL is activated to the high voltage Vpp, and data of the memory cell MC is output through the bit line pair BL, BLB. When the bit line sense enable signal PSE0 is activated, the internal power voltage is applied to the bit line sense amplifier BLSA, and the bit line sense amplifier BLSA senses and amplifies the data using the internal power voltage AIVC. Next, when the precharge signal PRC0 is activated, the word line is precharged to the precharge voltage Vbb.
FIG. 3 is a block diagram illustrating the internal power voltage generating circuit of the conventional semiconductor memory device whose memory cell array is comprised of four banks. The internal power voltage generating circuit of FIG. 3 includes a bank address decoder 22, four sensing signal generating portions 24-1 to 24-4, and an internal power voltage outputting portion 40. The internal power voltage outputting portion 40 includes an OR gate 42, a waveform generating portion 44, and an internal voltage driving portion 46.
Functions of the components of FIG. 3 are described below.
The bank address decoder 22 outputs bank selecting signals BS0 to BS3 in response to bank address signals BA0 and BA1 input from the external portion. The four sensing signal generating portions 24-1 to 24-4 output the bit line sense enable signals PSE0 to PSE3 in response to the row activation command RASB and the bank selecting signals BS0 to BS3 input from the external portion, respectively. The internal power voltage outputting portion 40 outputs the internal power voltage AIVC needed for sensing and amplifying data in response to the bit line sense enable signals PSE0 to PSE3.
The OR gate 42 outputs a sense master signal PSE-m in response to the bit line sense enable signals PSE0 to PSE3. That is, when at least one of the bit line sense enable signals PSE0 to PSE3 is activated, the sense master signal PSE-m is activated. The waveform generating portion 44 outputs a first control signal P1 in response to the sense master signal PSE-m. That is, the waveform generating portion 44 outputs the first control signal P1 which delays the sense master signal PSE-m during a predetermined time period and has a predetermined pulse width. The internal voltage driving portion 46 outputs the internal power voltage AIVC in response to the first control signal P1.
FIG. 4 is a timing diagram illustrating operation of the internal power voltage generating circuit of the conventional semiconductor memory device of FIG. 3. In FIG. 4, RASB denotes a row activation command, PSE0 and PSE1 denote bit line sense enable signals for activating the bit line sense amplifiers BLSA in the bank B0 and the bank B1, respectively, and P1 denotes a first control signal.
Operation of the internal power voltage generating circuit of the conventional semiconductor memory device of FIG. 3 is described below with reference to FIG. 4.
For purposes of this description, it is assumed that at a time point tithe row activation command RASB is input and an address signal corresponding to the bank B0 is input. Also, it is assumed that at a time point t2 the row activation command RASB is input and an address signal corresponding to the bank B1 is input. In response to the row activation command RASB input at the time point t1, after a predetermined time period is lapsed, the bit line sense enable signal PSE0 is activated, and in response to the row activation command RASB input at the time point t2, after a predetermined time period is lapsed, the bit line sense enable signal PSE1 is activated.
When the bit line sense enable signal PSE0 is activated, after a predetermined time period is lapsed, the first control signal P1 having a predetermined pulse width is output, and when the bit line sense enable signal PSE1 is activated, after a predetermined time period is lapsed, the first control signal P1 having a predetermined pulse width is output.
The internal voltage driving portion 46 operates by the first control signal P1 to supply the bit line sense amplifiers BLSA with the internal power voltage AIVC.
However, the internal power voltage generating circuit of the conventional semiconductor memory device has a problem in that it cannot boost the internal power voltage AIVC to a desired level when the semiconductor memory device operates at high speed.
That is, when the internal power voltage generating circuit outputs the internal power voltage AIVC and the bit line sense amplifier BLSA performs the sensing and amplifying operation using the internal power voltage AIVC, a level of the internal power voltage AIVC suddenly drops. That is, a dip occurs in the internal power voltage AIVC. However, after the row activation command RASB for the bank B0 is input, if the time required until the row activation command RASB for the next bank B1 is input is reduced, the internal power voltage AIVC applied to the bit line sense amplifier BLSA arranged in the bank B1 does not have a sufficiently high level due to the dip. Thus, it requires a large amount of time for sensing and amplifying data and the semiconductor memory device cannot operate at high speed.
FIG. 5 is a block diagram illustrating the high voltage generating circuit of the conventional semiconductor memory device. The high voltage generating circuit of FIG. 5 includes an OR gate 52, a waveform generating portion 54, and a high voltage driving portion 56. In FIG. 5, PSE0 to PSE3 denote bit line sense enable signals, and Vpp denotes a high voltage.
Functions of the components of FIG. 5 are described below.
The OR gate 52 outputs a master signal PRD in response to the bit line sense enable signals PSE0 to PSE3. That is, when at least one of the bit line sense enable signals PSE0 to PSE3 is activated, the master signal PRD is activated. The waveform generating portion 54 outputs a second control signal P2 in response to the master signal PRD. That is, the waveform generating portion 54 outputs the second control signal P2 which delays the master signal PRD during a predetermined time period and has a predetermined pulse width. The high voltage driving portion 56 outputs the high voltage Vpp in response to the second control signal P2. The high voltage Vpp is needed to activate the high voltage Vpp.
However, even in this case, when certain word lines are activated using the high voltage, the dip also occurs in the high voltage Vpp. For this reason, when attempts are made to sequentially activate other word lines, a level of the high voltage Vpp is sufficiently not boosted after a second attempt.
FIG. 6 is a block diagram illustrating the conventional precharge voltage generating circuit in a case where the memory cell array is comprised of four banks. The precharge voltage generating circuit of FIG. 6 includes a bank address decoder 22, four precharge signal generating portions 26-1 to 26-4, and a precharge voltage outputting portion 60. The precharge voltage generating portion 60 includes an OR gate 62, a waveform generating portion 64, and a precharge voltage pump 66.
Functions of the components of FIG. 6 are described below.
The precharge voltage generating portion of FIG. 6 has the same configuration as the internal power voltage generating circuit of FIG. 3 except that the row activation command RASB is replaced with the precharge command PRECH.
The bank address decoder 22 outputs bank selecting signals BS0 to BS3 in response to bank address signals BA0 and BA1 input from the external portion. The four precharge signal generating portions 26-1 to 26-4 output the precharge signals PRC0 to PRC3 in response to the precharge command PRECH and the bank selecting signals BS0 to BS3 input from the external portion, respectively. The precharge voltage generating portion 60 outputs the precharge voltage Vbb in response to the precharge signals PRC0 to PRC3.
The OR gate 62 outputs a precharge master signal PRC-m when at least one of the precharge signals PRC0 to PRC3 is activated. The waveform generating portion 64 outputs a third control signal P3 in response to the precharge master signal PRC-m. The precharge voltage pump 66 outputs the precharge voltage Vbb in response to the third control signal P3. The precharge voltage Vbb has a level smaller than zero (0) and is used to precharge the word line.
However, even in this case, when a plurality of word lines are sequentially precharged, a level of the precharge voltage Vbb is not adjusted to a desired level.
That is, the conventional semiconductor memory device with the multi-bank structure has a problem that a voltage level is not adjusted to a desired level to thereby lower an operation speed thereof when operation which requires a voltage of a predetermined level is continuously performed.